New Electronics

Microchip releases C++ synthesis suite for PolarFire FPGA algorithm development

Microchip Technology has added an HLS design workflow, called SmartHLS, to its PolarFire FPGA families to allow C++ algorithms to be directly translated to FPGA-optimised Register Transfer Level (RTL) ...
Semiconductor Engineering

Applying Machine Learning to EDA, FPGA Design Automation Tools

A technical paper titled “Application of Machine Learning in FPGA EDA Tool Development” was published by researchers at the University of Texas Dallas. “With the recent advances in hardware ...
Design-Reuse

How to use the CORDIC algorithm in your FPGA design

Most engineers tasked with implementing a mathematical function such as sine, cosine or square root within an FPGA may initially think of doing so by means of a lookup table, possibly combined with ...
GIGAZINE

'Algorithm Visualizer', a site where you can visually display algorithms and check them with code

When an algorithm is displayed in a program, it is difficult to imagine the program of the algorithm to be executed because the concept of the algorithm itself is complicated and partly because of ...