EDN

The battle over Verilog

Warning of possible industry “havoc,” Cadence Design Systems has sounded the alarm about possible incompatibility between System Verilog 3.1 and IEEE 1364 standard Verilog. Cadence's motives are ...
EDN

Likelihood of Verilog split is real

Warning of possible industry “havoc,” Cadence Design Systems has sounded the alarm about possible incompatibility between System-Verilog 3.1 and IEEE 1364 standard Verilog. Cadence's motives are ...
Electronic Design

Go Hybrid On AMS VerificationSponsored by: CADENCE DESIGN SYSTEMS

Meet in the Middle Although top-down analog/mixed-signal (AMS) design methodologies have been promoted by academia for many years, few people use them, especially in the U.S. Analog-flavored HDLs like ...