GitHub

GURUNANDINIDEVI/100-Days-Verilog-Coding

👩‍💻 Connect With Me If you’re passionate about VLSI, RTL Design, or Verilog, feel free to connect and collaborate!
GitHub

Senbagaseelan18/RISC-V-SOC-Tapeout-Week-1

Day 1 Introduction to RTL & Digital Design Combinational vs Sequential, RTL basics, Clocks & Resets, Verilog coding Learned fundamental concepts of digital design, RTL coding styles, and simulation ...
IEEE

VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding

Abstract: Large language models (LLMs) offer significant potential for coding, yet fine-tuning (FT) with curated data is essential for niche languages like Verilog. Using proprietary intellectual ...