I designed a 4-bit adder using the DE10-lite FPGA board. The core of this project was to implement an adder circuit that could handle 4-bit binary numbers. To achieve this, I utilized 8 switches on ...

Our findings underscore the considerable challenges faced by existing LLMs in VHDL code generation, revealing significant scope for improvement. This study emphasizes the necessity of supervised ...

In this study, we evaluate the performance of existing code LLMs for VHDL code generation and summarization using various metrics and two datasets - VHDL-Eval and VHDL-Xform. The latter, an in-house ...

VHDL code looks odd from a software programmer’s perspective because it’s closer to the hardware and strongly typed: an 8-bit integer isn’t the same as eight wires in VHDL.