Nuacht

Semiconductor Engineering2y

Scalable, Shared-L1-Memory Manycore RISC-V System

A new technical paper titled “MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory” was published by researchers at ETH Zurich and University of Bologna. “Shared L1 memory ...
Semiconductor EngineeringLíon na míonna: 1

Implementing Fast Barriers For A Shared-Memory Cluster Of 1024 RISC-V Cores

A technical paper titled “Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster” was published by researchers at ETH Zürich and Università di Bologna. “Synchronization ...