Sequential-Logic-Design Project Description The purpose of this project was to develop a circuit to cycle through a BCD encoding of a unique 9-digit value and display the aforementioned value on a ...

About Final design project for an Engineering Physics course at McMaster University. A finite-state machine that was designed using the ICs available to us and NI Multisim to produce a device that ...

As CMOS device sizes continue to scale down, radiation-related reliability issues are of ever-growing concern. Single event double node upsets (SEDUs) in sequential logic and single event transients ...

Because of rapid hardware design's evolution, hardware circuits are more complex. Hardware designer would not spend too much time to produce the circuits. One of hardware designers' problems is ...

In this paper, a ternary circuit design method that does not require cascading basic ternary logic gates is proposed based on a tri-valued memristor, which can directly realize specific logic ...

Touted as the industry's only sequential-logic equivalence checker, the SLEC platform enables design teams to quickly verify that RTL implementations match system-level specifications.