IEEE

Modification of Dynamic Logic Circuit Design Technique for Minimizing Leakage Current and Propagation Delay

Abstract: This paper is based on the OR logic operation’s small discharging current and transmission time delay dynamic logic circuit configuration method. In terms of static logic circuits, it ...
TechRepublic

Logic Circuit Design Based on Series-Connected CMOS-NDR Circuit

In this paper, the authors propose a MOS-BJT-NDR circuit, which can show the Negative-Differential-Resistance (NDR) characteristic in its current-voltage curve. This NDR circuit is composed of ...
IEEE

Worst-Case Considerations in Designing Logical Circuits

Abstract: A method of design is presented for logical circuits, starting from worst-case considerations. The method represents an approach to dc optimization. Special attention is paid to temperature ...
GitHub

logic-circuit-design

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level.
EE Herald

Advanced VLSI design: Use of qubits in logic circuit design

One of the most promising nanotechnologies which can replace the present transistor based CMOS technology is the Qubit (Quantum-Dot) Cellular Automata. The major advantages of this technology are ...
GitHub

A digital logic circuit project demonstrating foundational computer science principles, including Boolean algebra, truth tables, and Karnaugh map simplification. The circuit ...

There was an error while loading. Please reload this page. Logic Circuit Design for an Asian Recipe Selector This repository contains a digital logic circuit design ...
Electronic Design

For Designers: Logic Nets in Transistor Cans (ED article from 1961)

March 29, 1961 - LOGICAL microcircuits in transistor cans are now being offered by four major companies. Heavy research and production is being pressed by Fairchild Semiconductor Corp., Raytheon Co., ...