Design-Reuse

Parallel Turbo decoder for LTE and LTE-A

This block is suitable for 3GPP Long Term Evolution (LTE) applications compatible with the 3GPP Technical Specification. The LTE Release-8 Turbo code achieves near optimal error-correcting performance ...
Design-Reuse

3gpp lte turbo decoder IP Listing

TC7000-LTE is a convolutional turbo code (CTC) decoder optimized for FPGAs. Its unique pipe-line architecture enables to reach very high clock frequencies on high end FPGAs It offers several ...
EDN

Xilinx Meets Performance Requirements of LTE Wireless Systems With New LogiCORE Turbo Encoder and Decoder Solu

Xilinx Meets Performance Requirements of LTE Wireless Systems With New LogiCORE Turbo Encoder and Decoder SolutionsDelivers 5X throughput boost to developers of next-generation wireless systems ...
IEEE

A multi-mode 3GPP-LTE/HSDPA turbo decoder

Abstract: The LTE standard supports a maximum throughput of 300MBit/s using 4×4 MIMO and a channel bandwidth of 20 MHz. At the same time the latest HSDPA technology supports 82MBit/s using 2×2 MIMO ...
EDN

Lattice expands wireless solutions with 3FPP-LTE CTC decoder IP core

The folks at Lattice have announced the availability of a 3GPP-Long-Term Evolution (LTE) Convolutional Turbo Code (CTC) Decoder intellectual property (IP) core from TurboConcept, a member of the ...
Electronic Specifier

Tensilica Announces Availability of Atlas Reference Architecture Dataplane Processors for a Complete Baseband PHY for LTE, HSPA+ and WiMAX

Tensilica announced that all the optimized programmable DPUs (dataplane processing units) of its Atlas Reference Architecture are now available for customer evaluation. The Atlas Reference ...
Electronic Design

LTE Comm Processor Implements Mutli Dispatch VLIW Architecture

Tensilica has delivered a range of processor architectures like the Xtensa LX (see Power Play For The SoC Developers) as well as DSP and the ConnX comm processor (see Dataplane Processing Unit More ...