IEEE

A Minimal-Resource LDPC Encoder and Decoder Design for Memory-Constrained Systems

Abstract: In this paper we present our LDPC encoder and decoder design focused on, but not limited to, the LDPC codes described in the recent CCSDS space data systems standard, known as the Blue Book.
Design-Reuse

Creonic to Supply New LDPC Decoder and Encoder IP Cores for CCSDS Standard

Kaiserslautern, Germany, Apr. 30 2015 – Creonic GmbH, a leading IP core provider for communications, announced today the release of their new CCSDS LDPC encoder and decoder IP cores for the satellite ...
Design-Reuse

Creonic to Provide Three LDPC Decoder IP Cores for DOCSIS 3.1

Kaiserslautern, Germany, Oct. 28, 2015 - Creonic GmbH, a leading IP core supplier for communications, revealed today the availability of three IP cores for the new DOCSIS 3.1 standard. DOCSIS 3.1 ...
IEEE

Design and Analysis of the Tail Sequence for Short LDPC-Coded Space Communications

Abstract: According to some standards for satellite communications, the transmitted stream is divided into transmission units with variable length, for which detecting the termination is particularly ...
Fujitsu

LDPC（Low Density Parity Check）

低密度パリティ検査（Low Density Parity Check : LDPC）は，1962年にRobert G. Gallager氏によって提案されたのが始まりです。当時は、符号長（n）が大きいと計算量が莫大になるなどの理由で忘れ去られてしまいましたが、その後1999年にMacKayらによってシャノン限界に ...
GitHub

Releases: mahekjikkar/5G-NR-LDPC-Decoding-in-MATLAB

You can create a release to package software, along with release notes and links to binary files, for other people to use. Learn more about releases in our docs.
マイナビニュース

LSI、40nm LDPCのデコードに対応したデコーダチップを発表

米LSIは、「TrueStore RC9700」を発表した。これは40nmのRead Channelに対応したLDPC Decoderの第2世代製品となり、すでにHDDメーカーにサンプル出荷を開始している。 RC9700はノートブックPCからデスクトップPC、エンタープライズまで幅広い価格レンジに対応し、高性能 ...
INTERNET Watch

電圧レベルは16段階に、増えたエラーは強力な「LDPC」で対策するも ...

1000BASE-Tの10倍速、という高速な有線LAN規格「10GBASE-T」が、いよいよ身近になりつつある。 LANカードは既に100ドル以下のモデルや2万円台のモデルが登場、ハブについても8ポート8万円の製品が国内で発売済み。10GBASE-T標準搭載のiMac Proも12月に発売されるなど ...
Total Telecom

AccelerComm’s New Highly Optimised LDPC Decoder in Software for Intel’s FlexRAN ...

AccelerComm, the company supercharging 5G with Optimisation and Latency Reduction IP, today announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The ...
EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
New Electronics

AccelerComm develops LDPC Decoder for Intel’s FlexRAN

AccelerComm, the company specialising in optimisation and latency reduction IP, has announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The solution is ...