An appendix covers how to write your own operating system for RISC-V in about 1,000 lines of code. Don’t speak Japanese? An English version is available free on the Web and on GitHub.

Western Digital has announced that it's completed work on its "Swerv" RISC-V CPU core and has published the register-transfer level (RTL) abstraction of the design.

It also performs really well in terms of performance and code size. Icing on the cake, Codasip Studio generates other outputs such as executable models, RTL, or verification tools that complete the IP ...

Sounding the alarm For a RISC-V design to be compatible with another ISA requires huge amounts of verification compatibility tests. “RISC-V is not advocating compliance in the same way that an Arm ...

RISC-V’s open nature also reduces vendor lock-in, enabling faster innovation across automotive, AI, security, and high-performance computing (HPC). Andes Technology, a Founding Premier Member of ...