The RISC-V Summit drew about 1,000 people to San Jose, California, this week to hear the latest on the open-source processor.

With Synopsys ARC-V Processor IP, customers will benefit from optimized and configurable implementations and the flexibility to leverage this extensive RISC-V ecosystem, which will help achieve their ...

RISC-V offers a level of flexibility to design new processors because the instruction set isn’t defined at the ISA level, but rather is the compilation of the processor and other ...

Bluespec Inc. today announced its new MCUX RISC-V processor that makes it easy for developers to implement custom instructions and add accelerators to ...

Synopsys announced its plans for expanding its processor intellectual property portfolio with the new RISC-V ARC-V family.

SiFive's RISC-V CPU cores will sit at the heart of NASA's future spaceflight processor.

A group of prominent chipmakers is forming a new venture to broaden the adoption of the RISC-V processor architecture. The venture, which was unveiled by its backers this morning, will initially ...

AI is risky business A group of Chinese scientists has published (PDF) a paper titled Pushing the Limits of Machine Design: Automated CPU Design with AI in which they tell the epic adventure of ...

Verifying an SoC is very different than verifying a processor due to the huge state space in the processor. In addition to the tools needed for an SoC, additional tools are required for a step and ...

Unleash the power of RISC-V with the Orange Pi RV2. A $40 SBC designed for IoT, AI, and specialized applications.

Given that they are using a bit sequential RISC-V design, I wonder if they are using SERV or at least drawing inspiration from it.

With RISC, a central processing unit (CPU) implements the processor design principle of simplified instructions that can do less but can execute more rapidly. The result is improved performance.