EDN

Agere to pull Cadence partitioning, sign-off tool into ASIC flow

ALLENTOWN, Pa. — Agere Systems is working with San Jose, California-based Cadence Design Systems Inc. to provide Agere ASIC customers with access to Cadence's “First Encounter” EDA software. This is ...
EDN

Agere Collaborates with Cadence for ASIC Design Kit

Agere Systems Inc. today announced it has contracted with Cadence Design Systems Inc. to provide its ASIC customers with a temporary license to use Cadence's First Encounter design tool. Agere expects ...
Business Wire

Socionext Adopts the Cadence Full-Flow Digital and Signoff Tools for 7nm Designs

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Socionext used the Cadence ® full-flow digital and signoff tools for the successful production ...
Business Wire

GUC Optimizes Quality of Results and Accelerates Time to Tapeout Using the Cadence Digital Full Flow

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced Global Unichip Corporation (GUC) used the Cadence ® digital full flow to accelerate the time to tapeout ...
Design-Reuse

Cadence Boosts Verification Productivity for Complex FPGA/ASIC Design

SAN JOSE, Calif. -- Jan 10, 2011 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, today announced significant new advancements to help boost ...
Nasdaq

Cadence’s New Flow Automates Custom/Analog Design Migration on TSMC Advanced Technologies

Companies to enable easy node-to-node migration for analog blocks with enhanced PDK across multiple FinFET processes to accelerate design closure Early customers seeing more than 2.5X design cycle ...
Electronic Design

Fujitsu ships production volumes of structured ASIC

Cadence Design Systems and Fujitsu Microelectronics America (FMA) have announced that FMA is shipping initial production volumes of a new, complex, structured ASIC using Cadence Encounter IC ...