ニュース

EDN1年

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To ...
Electronic Design1年

Hardware Compression Works at the Memory Cache Level - Electronic Design

ZeroPoint’s CacheMX, which works at the cache level, is IP that’s included with a processor’s IP. The lossless compression system also manages the compressed data (Fig. 1).
Design-Reuse7月

Cache memory design in verilog IP Listing

The CCRV32ST-S is a synthesisable Verilog model of a high performance 32-bit RV32GC System-on-Chip. The model is highly configurable and embeds a wide range of peripherals.