Over on the University of Reddit there’s a course for learning all about FPGAs and CPLDs. It’s just an introduction to digital logic, but with a teacher capable of building a CPLD motor control board ...

Altium has expanded support for system-level FPGA and CPLD development by adding a JTAG interface to its Nexar system. The addition of the JTAG port enables engineers to use their FPGA-development ...

In its third major and field-programmable gate array (FPGA) announcement in the last 12 months, Lattice Semiconductor Corp. has introduced MachXO, a new product family that combines the key features ...

Designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function ...

Adding to the CoolRunner-II CPLD family, the XC2C32A and XC2C64A debut in smaller MLF packages than their predecessors and integrate an additional I/O bank to support voltage level translation and ...

These programmable-logic devices combine CPLD flash configurability with an FPGA lookup-table architecture for lower-cost, logic-intensive designs. Applications traditionally supported by high-density ...

HILLSBORO, OR - August 30, 2005 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that RAD Data Communications has selected the LatticeECâ„¢ FPGA as well as the ispMACHâ„¢ 4000 CPLD ...

[PK] is working on a very simple video card, meant to output 640×480 VGA with a cheap CPLD. The interface will be 5 Volt SPI, meaning there’s a ton of potential here for anyone wanting put a ...

SAN JOSE, Calif., Oct. 11, 2011-- Altera Corporation today unveiled its family of ARM-based SoC FPGAs, integrating 28-nm Cyclone® V and Arria® V FPGA fabric, a ...

Intel refreshed its FPGA line-up with cost-optimized offerings, released its FPGA software stack as open source, and added a new processor design based on the RISC-V architecture. The first of the new ...