EDN

Flip-Flop Using CMOS NAND Gates

Using just two NAND or inverter gates its possible to build a D type (or ‘toggle’) flip-flop with a push-button input. At power-up the output of gate N2 is at a logical ‘1’, ensuring that transistor T2 ...
IEEE

A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate

Abstract: The primary goal of this work is to develop a low-level physics-based nonquasi-static MOSFET model that can be extended to the simulation of high-level CMOS logic circuits. In this part of ...
GitHub

CMOS Circuit Design and SPICE Simulation using SKY130 Technology Workshop

This ten-day workshop, organized by VLSI System Design, was centered on CMOS circuit design and SPICE simulation using SKY130 technology. The sessions were structured progressively, beginning with the ...
Electronic Design

Six MOSFETs, Four Pins Create Two-Input Combo NAND/NOR Gate

This CMOS two-input combination NAND/NOR gate is a three-input, fourpin logic gate. A p-channel enhancementtype MOSFET (Q1) and an n-channel enhancement-type MOSFET (Q4) form one complementary ...
IEEE

A Comparative Analysis of 4:1 Multiplexer Design Using 2:1 Multiplexers in Terms of Delay and Power

Abstract: NAND gates, as they are implemented by 180nm, 90nm, and 45nm CMOS technologies also in SCL180, are applied in this work to construct and study a 4:1 multiplexer (MUX). each of which is built ...
Digi Times

Samsung introduces new fusion NAND flash, 64GB SSD and 8.4-megapixel CMOS image sensor

Samsung Electronics unveiled today at the 2007 Samsung Mobile Solution Forum in Taipei a new fusion NAND, Flex-OneNAND, 64GB solid-state disk (SSD) and a 8.4-megapixel CMOS image sensor. Save my User ...