This project implements an 8-bit signed Booth multiplier in Verilog, capable of multiplying two signed integers and producing a 16-bit signed product. It follows Booth's Algorithm for signed binary ...
... test_booth_core(0, +42, +13); test_booth_core(1, -42, +13); test_booth_core(2, +42, -13); test_booth_core(3, -42, -13); ...
Abstract: This paper presents a three-integers multiplication algorithm R = A * X * Y for Reconfigurable Mesh (RM). It is based on a three-integer multiplication algorithm for faster FPGA ...
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