Santa Cruz, Calif. – Claiming a new capability for chip designers, startup Bluespec Inc. this week will announce its ability to synthesize SystemVerilog verification assertions into Verilog 1995 RTL ...

Design-for-verification (DFV) using assertions has received much attention in the recent technical press. Coverage has ranged from standardization efforts for assertion languages to complete DFV ...

Adds Support for SystemVerilog Assertions, Flexible Probes, Waveform Generation With Combinational Signals SAN JOSE, CALIF. –– April 13, 2009 –– EVE , the leader in hardware/software ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...

Database upgrades, clock-tree and timing debug features, and support for assertion-driven debugging have all been added to Novas' debug systems. In the latest versions of its Debussy and Verdi ...