This paper presents an 8-bit 1.6GS/s successive-approximation-register analog-to-digital converter (SAR ADC) with alternate comparators. To enhance dynamic performance and speed, a dither-based ...

A new voltage-mode comparator circuit for use in CMOS multiple-valued logic circuits is introduced. Existing comparator circuits for this application use static current or clocking and thus consume ...

Write a Verilog HDL program in Hierarchical structural model for a) 16:1 multiplexer realization using 4:1 multiplexer b) 3:8 decoder realization through 2:4 decoder c) 8-bit comparator using 4-bit ...