IEEE

Low-power VLSI decoder architectures for LDPC codes

Abstract: Iterative decoding of low-density parity check codes (LDPC) using the message-passing algorithm have proved to be extraordinarily effective compared to conventional maximum-likelihood ...
IEEE

A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes

Abstract: This paper presents a VLSI implementation of a Low-Density Parity Check (LDPC) decoder that achieves 2.4 Gbps throughput yet permits real-time configuration of (1) rate, (2) code length, and ...