GitHub

Gribbl3/3-to-8-decoder-vhdl

This repository contains VHDL code for a 3-to-8 decoder with a main component. The decoder takes a 3-bit input and generates an 8-bit output based on the input. The main component instantiates two ...
GitHub

saiyra87/Simple-VHDL-CPU

This project involves designing and implementing a simple Central Processing Unit (CPU) in VHDL for deployment on an FPGA board. The CPU is composed of two primary components: the Arithmetic Logic ...
IEEE

Design and implementation of list-of-2 Viterbi decoder with VHDL and its application

Abstract: To use list Viterbi decoding (LVA) as inner decoder with error detection outer codes, the list size must be large enough to almost always include the ...