GitHub

Two-Bit-Comparator-Layout-A-Step-by-Step-Guide-Using-Ledit

This project was part of the Advanced VLSI (AVLSI) course I took in Winter 2024 at the University of Guilan. It was a great learning experience under the guidance of Dr. Aminian, aimed at deepening my ...
GitHub

nishit0072e/2bit-Comparator

In the diagram, a 2-bit magnitude comparator is split into two blocks: digital and analog. The digital portion of the circuit is implemented using Verilog. For the analog portion, the two 3-input ”OR” ...
IEEE

A Novel Hybrid CMOS-Memristor Based 2-Bit Magnitude Comparator using Memristor Ratioed Logic Universal Gate for Low Power Applications

Abstract: In recent years, memristor-based digital circuit design has become one of the prime focuses for low power, area-efficient VLSI design. A comparator is a combinational circuit used in complex ...
Scientific Research Publishing

Design of Low Power Comparator Using DG Gate ()

Department of Electrical Engineering, Sarvestan Branch, Islamic Azad University, Sarvestan, Iran. Department of Electrical Engineering, Zarghan Branch, Islamic Azad University, Zarghan, Iran. Young ...
Scientific Research Publishing

Design and Implementation of an Efficient Reversible Comparator Using TR Gate ()

1 Department of EEE, P. S. G. College of Technology, Coimbatore, India. 2 Sri Eshwar College of Engineering, Kondampatty, India. Reversible logic is a new emerging technology with many promising ...
EDN

Understanding precision comparator applications (Part 1 of 2)

The comparator is a high-gain amplifier that is used to amplify a small differential signal at its input, and drive the output to one of two output states. Figure 1 shows the basic comparator circuit, ...
IEEE

Design of CMOS 8-BIT Comparator for Low Power Application

Abstract: In this paper we have presented two different designs for 8-bit comparator, one is conventional comparator and other is low power comparator. First of all we have designed conventional ...
EDN

Using auto-zero comparator techniques to improve PWM performance (Part 1 of 2)

Comparators are subject to input offset errors that can be either systematic or layout related. Two applications of comparators in a PWM controller are detecting when there is no current in the ...
Frontiers

Ternary combinational logic gate design based on tri-valued memristors

Traditional binary combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and complicated wiring. In contrast to the binary logic ...