Design-Reuse

Xilinx IP Solutions Division Standardizes on Model Technology's Simulation Tool, ModelSim

PORTLAND, Ore.--Nov. 28, 2000--Xilinx, Inc. and Model Technology, a Mentor Graphics company, today announced that the Intellectual Property (IP) Solutions Division of Xilinx has standardized on ...
Design-Reuse

Xilinx and EV Engineering deliver MHz co-simulation with Virtex-II technology

Based on the advanced Virtex-IITM FPGAs ZeBu accelerates co-simulation of designs driven by Verilog/VHDL/C/C++/SystemC testbenches PARIS, France, April 22, 2002 ...
Electronic Design

Tool Increases Simulation Speed For Xilinx PGAs

Developed specifically for Xilinx devices, the Active-HDL 4.2XE achieves a 40% increase in simulation speed over the previous, 4.0XE version.With the new tool, users have the ability to seamlessly ...
GitHub

Releases: TharunbabuC/RTL-Based-Digital-Design-and-Simulation-using-Verilog-and-XILINX-SOFTWARE

You can create a release to package software, along with release notes and links to binary files, for other people to use. Learn more about releases in our docs.
Ars Technica

Open Source VHDL (or similar) CPU Simulation Software

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...
EDN

Synopsys speeds Verilog, VHDL simulation

MOUNTAIN VIEW, Calif. — Claiming substantial speedups in its Verilog and VHDL simulation products, Synopsys Inc. this week is announcing releases of its VCS Verilog and Scirocco VHDL simulators. The ...
EDN

VHDL simulator flags inadequately tested code

The CoValidator VHDL simulator and coverage analyzer, the first component of Impulse's forthcoming CoDeveloper hardware/software design suite, enables users to quickly identify specific lines of code ...