Traditionally, external SRAMs feature a parallel interface. Given the memory requirements for most of SRAM-based applications, it’s no surprise that parallel is a better option. For the high ...

This article analyzes system design specifications for a low-voltage differential serial output interface of a multi-channel, high-speed analog-to-digital (A/D) converter. Maximum data speed is ...

This document provides information about the F-Tile Avalon® Streaming IP for PCI Express Configuration Intercept Interface (CII) interface. The document details an example design that demonstrates CII ...